In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities, there has been and continues to be efforts toward scaling down device dimensions (e.g., at submicron levels) on semiconductor wafers. In order to accomplish such high device densities, smaller and smaller feature sizes are required that include, for example, the width, depth, and spacing of interconnecting lines, spacing and size of memory cells, and surface geometry of various: features such as corners and edges. Such small feature characteristics require high-resolution photolithographic processes for pattern transfer between various media. A wafer is coated uniformly with a radiation-sensitive photoresist film, and an exposing source (such as optical light, x-rays, or an electron beam) illuminates selected areas of the wafer surface through an intervening master template mask for a particular pattern.
Layers of photoresist, conductive, polymeric and insulative materials are routinely applied to wafers multiple times during a manufacturing process for integrated circuits, as one of a sequence of steps to produce a desired lithographic pattern. Thickness and uniformity of the layers is critical to the overall functionality of the manufactured device. The goal of the photoresist application process as well as subsequent layering processes is to achieve uniform layers on the wafer surface. This goal can be achieved by planarizing the layers in order to obtain a desired thickness and uniformity.
Metal silicides have excellent material properties. For example, a cobalt alloy (CoSi2) has a very low resistivity, ability of uniform formation on very narrow polycrystalline-silicon (“poly-Si”) lines, no reaction with dopants, and good resistance to dry etching. When cobalt silicide is applied in self-aligned processes, device operating speeds can be increased. However as devices are scaled down to deep submicron dimensions, the formation of stable and very shallow junctions which is essential to successful device fabrication becomes more difficult.
Silicide formation occurs in conjunction with an annealing process where the wafer is heated for a short period of time to form a metal silicide. Some silicidation processes may be performed in multiple annealing steps, for example, when using titanium (TiSi2).
What is needed are improved silicidation processes in semiconductor fabrication.